4-mbit (1m x 4) static ram CY7C1046DV33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05611 rev. *b revised april 3, 2006 features ? pin- and function-compatible with cy7c1046cv33 ?high speed ?t aa = 10 ns ? low active power ?i cc = 90 ma @ 10 ns ? low cmos standby power ?i sb2 = 10 ma ? 2.0 v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features ? available in lead-free 400-mil-wide 32-pin soj package functional description [1] the CY7C1046DV33 is a high-performance cmos static ram organized as 1m words by 4 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the four i/o pins (i/o 0 through i/o 3 ) is then written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the four input/output pins (i/o 0 through i/o 3 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the CY7C1046DV33 is available in a standard 400-mil-wide 32-pin soj package with center power and ground (revolu- tionary) pinout. selection guide 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 1 mbit x 4 i/o 3 i/o 2 a 0 a 11 a 13 a 12 a ce a a 16 a 17 1 2 3 4 5 6 7 8 9 10 12 21 22 25 24 23 28 27 26 top view soj 11 29 32 31 30 14 13 19 20 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 i/o 2 a 9 a 0 i/o 0 i/o 1 oe a 17 a 16 a 13 ce a 9 a 18 16 15 17 18 gnd i/o 3 v cc a 10 a 11 a 19 nc a 10 a 19 -10 unit maximum access time 10 ns maximum operating current 90 ma maximum cmos standby current 10 ma note: 1. for guidelines on sram system design, please refer to the system design guidelines cypress application note, available on the internet at www.cypress.com. [+] feedback [+] feedback
CY7C1046DV33 document #: 38-05611 rev. *b page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc to relative gnd [2] .......?0.3 to +4.6v dc voltage applied to outputs in high-z state [2] .....................................?0.3v to v cc +0.3v dc input voltage [2] ................................. ?0.3v to v cc +0.3v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ...... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc industrial ?40c to +85c 3.3v + 0.3v dc electrical characteristics over the operating range parameter description test conditions -10 unit min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 100 mhz 90 ma 83 mhz 80 66 mhz 70 ma 40 mhz 60 i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 20 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 10 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.3v 8 pf c out i/o capacitance 8 pf thermal resistance [3] parameter description test conditions soj package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 53.44 c/w jc thermal resistance (jun ction to case) 38.25 c/w notes: 2. v il (min.) = ?2.0v and v ih (max) = v cc +2v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters [+] feedback [+] feedback
CY7C1046DV33 document #: 38-05611 rev. *b page 3 of 8 ac test loads and waveforms [4] ac switching characteristics over the operating range [5] parameter description -10 unit min. max. read cycle t power [6] v cc (typical) to the first access 100 s t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce low to data valid 10 ns t doe oe low to data valid 5 ns t lzoe oe low to low-z [8] 0ns t hzoe oe high to high-z [7, 8] 5ns t lzce ce low to low-z [8] 3ns t hzce ce high to high-z [7, 8] 5ns t pu ce low to power-up 0 ns t pd ce high to power-down 10 ns write cycle [9, 10] t wc write cycle time 10 ns t sce ce low to write end 7 ns t aw address set-up to write end 7 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 7 ns t sd data set-up to write end 5 ns t hd data hold from write end 0 ns t lzwe we high to low-z [8] 3ns t hzwe we low to high-z [7, 8] 5ns notes: 4. ac characteristics (except high-z) are tested using the load conditions shown in (a). high-z characteristics are tested for a ll speeds using the test load shown in (c). 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 6. t power gives the minimum amount of time that the power supply should be at stable, typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (c) of ac test loads. transition is measured when the outputs enter a high impedance state. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment (b) rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z=50 ? 50 ? 1.5v (a) 3.3v output 5 pf (c) r 317 ? r2 351 ? high-z characteristics: [+] feedback [+] feedback
CY7C1046DV33 document #: 38-05611 rev. *b page 4 of 8 data retention characteristics over the operating range parameter description conditions [11] min. max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 10 ma t cdr [3] chip deselect to data retention time 0 ns t r [12] operation recovery time t rc ns data retention waveform 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms read cycle no. 1 [13, 14] read cycle no. 2 (oe controlled) [14, 15] notes: 11. no inputs may exceed v cc + 0.3v 12. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s 13. device is continuously selected. oe , ce = v il . 14. we is high for read cycle. 15. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current [+] feedback [+] feedback
CY7C1046DV33 document #: 38-05611 rev. *b page 5 of 8 write cycle no. 1 (ce controlled) [16, 17] write cycle no. 2 (we controlled, oe high during write) [16, 17] notes: 16. data i/o is high impedance if oe = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 18. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 18 [+] feedback [+] feedback
CY7C1046DV33 document #: 38-05611 rev. *b page 6 of 8 write cycle no. 3 (we controlled, oe low) [17] truth table ce oe we i/o 0 ? i/o 3 mode power h x x high-z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high-z selected, outputs disabled active (i cc ) switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 18 [+] feedback [+] feedback
CY7C1046DV33 document #: 38-05611 rev. *b page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentioned in this documen t may be the trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1046DV33-10vxi 51-85033 32-lead (400-mil) molded soj (pb-free) industrial please contact your local cypress sales representative for availability of these parts. package diagram 32-pin (400-mil) molded soj (51-85033) 51-85033-*b [+] feedback [+] feedback
CY7C1046DV33 document #: 38-05611 rev. *b page 8 of 8 document history page document title: CY7C1046DV33 4-mbit (1m x4) static ram document number: 38-05611 rev. ecn no. issue date orig. of change description of change ** 307613 see ecn rkf new data sheet *a 397134 see ecn rxu changed from advance to preliminary changed address of cypress semicondu ctor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed -15 speed bin corrected dc voltage limits in maximu m ratings section from - 0.5 to - 0.3v and v cc + 0.5v to v cc + 0.3v redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 100, 80 and 70 ma to 90, 80 and 75 ma for 8, 10 and 12ns speed bins respectively i cc (ind?l): changed from 80 and 70 ma to 90 and 85 ma for 10 and 12ns speed bins respectively removed footnote on rise time and added footnote on operation recovery time (t r ) corrected typo in truth table from (i/o 0 - i/o 7) to (i/o 0 to i/o 3) changed part names from v33 to v32 in the ordering information table removed l-version added lead-free product information shaded ordering information table *b 459072 see ecn nxr converted from preliminary to final removed -8 and -12 speed bins removed commercial operating range product information removed the pin definition table changed the capacitance value of input pins and i/o pins from 6 pf to 8 pf updated the thermal resistance table updated footnote #7 on high-z parameter measurement added footnote #11 replaced package name column with package diagram in the ordering information table [+] feedback [+] feedback
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